The IEEE 1149.4 mixed signal test bus standard [Reference 1], approved by the IEEE in 1999, mainly focuses on analog interconnect testing at board level. It experiences difficulties in providing high-frequency functional testing due to its insufficient bandwidth caused by the parasitic effects of the long multi-drop analog bus [Reference 2] as shown in FIG. 1. Nevertheless, it provides a common platform for further development.
IEEE Std. 1149.4 relies on two analog buses, AB1/AT1 and AB2/AT2, to transfer test stimuli and responses. The most significant side effect for using multi-drop buses is the limited bandwidth. Sunter et al. [Reference 3] improves the frequency response by redesigning analog boundary module (ABM) and test bus interface circuit (TBIC). With which, the signal frequency can be as high as 10 MHz. Su et al. [Reference 2] takes a digital signal processing (DSP) approach to eliminate the parasitic effects via the de-convolution. Acevedo et al. [Reference 4] proposed a VDDQ built-in self-test (BIST) architecture to compare the quiescent voltage of the circuit nodes with a pre-stored voltage to determine the pass/fail of the circuit. Su et al. [Reference 5] uses the dual comparators in TBIC to quantize the quiescent voltage and statistical method to obtain the DC offset voltage. Su et al. and Sunter et al. [References 2,3] focus on frequency response improvement, and Acevedo et al. and Su et al. [References 4,5] work on the quiescent voltage measurement. None of them can handle the dynamic test issue in BIST.